HANBit
HMN1288J
URL: www.hbe.co.kr
5
HANBit Electronics Co.,Ltd.
Rev.0.0 (FEBRUARY/ 2002)
WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax )
-70
-85
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
UNIT
Write Cycle Time
tWC
55
-
70
-
ns
Chip enable to end of write
tCW
Note 1
45
-
60
-
ns
Address setup time
tAS
Note 2
0
-
0
-
ns
Address valid to end of write
tAW
Note 1
45
-
60
-
ns
Write pulse width
tWP
Note 1
40
-
50
-
ns
Write recovery time (write cycle 1)
tWR1
Note 3
5
-
5
-
ns
Write recovery time (write cycle 2)
tWR2
Note 3
15
-
15
-
ns
Data valid to end of write
tDW
20
-
25
-
ns
Data hold time (write cycle 1)
tDH1
Note 4
0
-
0
-
ns
Data hold time (write cycle 2)
tDH2
Note 4
0
-
0
-
ns
Write enabled to output in high Z
tWZ
Note 5
0
20
0
25
ns
Output active from end of write
tOW
Note 5
5
-
5
-
ns
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*1,2
- READ CYCLE NO.2 (/CE Access)*1,3,4
Address
DOUT
Data Valid
tOH
tACC
tRC
Previous Data Valid
tACE
tCLZ
tRC
tCHZ
/CE
High-Z
High-Z
DOUT
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