EM39LV040

4M (512Kx8) Bits Flash Memory

SPECIFICATION

Timing Diagrams

Read Cycle Timing Diagram

HIGH-Z

HIGH-Z

Data Valid

Data Valid

A18~A0

CE#

OE#

WE#

DQ7-0

Figure 1: Read Cycle Timing Diagram

WE# Controlled Program Cycle Timing Diagram

5555

2AAA

5555

ADDR

Internal Program Operation Starts

AA

55

A0

DATA

SW0

SW1

SW2

Byte

(ADDR/DATA)

WE#

OE#

CE#

DQ7-0

A18~A0

Figure 2: WE# Controlled Program Cycle Timing Diagram

This specification is subject to change without further notice. (07.22.2004 V1.0)

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