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HM51W18165TT-7 Datasheet(PDF) 6 Page - Hitachi Semiconductor |
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HM51W18165TT-7 Datasheet(HTML) 6 Page - Hitachi Semiconductor |
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6 / 36 page  HM51W16165 Series, HM51W18165 Series 6 RAS LCAS UCAS WE OE Output Operation H D D D D Open Standby L L H H L Valid Lower byte Read cycle L H L H L Valid Upper byte L L L H L Valid Word LL H L* 2 D Open Lower byte Early write cycle LH LL* 2 D Open Upper byte LL LL* 2 D Open Word LL H L* 2 H Undefined Lower byte Delayed write cycle LH LL* 2 H Undefined Upper byte LL LL* 2 H Undefined Word L L H H to L L to H Valid Lower byte Read-modify-write cycle L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word L H H D D Open Word RAS-only refresh cycle H to L H L D D Open Word CAS-before-RAS refresh cycle or H to L L H D D Open Word Self refresh cycle (L-version) H to L L L D D Open Word L L L H H Open Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. This Material Copyrighted By Its Respective Manufacturer |
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