4

READ CYCLE

from the latter of device enable, output enable, or valid address

to valid data output.

An address access read is initiated by a change in address inputs

while the chip is enabled with OE asserted and PE deasserted.

Valid data appears on data output, DQ(7:0), after the specified

cycle. As long as device enable and output enable are active, the

address inputs may change at a rate equal to the minimum read

cycle time.

The chip enable-controlled access is initiated byCE going active

while OE remains asserted, PE remains deasserted, and the

addresses remain stable for the entire cycle. After the specified

t

appears at the data outputs DQ(7:0).

Output enable-controlled access is initiated by OE going active

while CE is asserted, PE is deasserted, and the addresses are

not been satisfied.

AC CHARACTERISTICS READ CYCLE (Post-Radiation)*

Notes:

* Post-radiation performance guaranteed at 25

°C per MIL-STD-883 Method 1019 at 1E6 rads(Si).

1. Functional test.

2. Three-state is defined as a 400mV change from steady-state output voltage.

SYMBOL

PARAMETER

28F256-45

MIN

MAX

28F256-40

MIN

MAX

UNIT

1

Read cycle time

45

40

ns

Read access time

45

40

ns

2

Output hold time

0

0

ns

2

OE-controlled output enable time

0

0

ns

OE-controlled access time

15

15

ns

t

GHQZ

OE-controlled output three-state time

15

15

ns

2

CE -controlled output enable time

0

0

ns

t

ELQV

CE -controlled access time

45

40

ns

CE-controlled output three-state time

15

15

ns