Detailed Description

Figure 2 is a functional diagram of the MAX3274 limit-

ing amplifier. Typical gain is 46dB. A linear input drives

a bandwidth selector. An offset correction loop with

lowpass filtering ensures low deterministic jitter. An

integrated RMS signal detector monitors for loss-of-sig-

nal conditions. The output buffer provides a limited

CML output signal.

Input Buffer

The MAX3274 input buffer (Figure 3) provides a 100

Ω

input impedance between IN+ and IN-. DC-

coupling the inputs is not recommended; doing so pre-

vents proper functioning of DC offset correction circuitry.

Signal Detect and Loss-of-Signal

An RMS signal detector looks at the signal from the

input buffer and compares it to a threshold set by a

resistor at pin TH. The status of the signal-detect infor-

mation appears at the LOS outputs. These are open-

collector outputs and require external pullup resistors

connected to the host power supply. The LOS outputs

are high impedance when the power supply to the

MAX3274 is 0V. ESD protection on the dual-rate limiting

amplifiers’ LOS outputs do not forward-bias when the

power supply of the MAX3274 is 0V or below the host

power supply.

Offset Correction

A low-frequency feedback loop is integrated into the

limiting amplifiers to reduce input offset and thereby

minimize duty-cycle distortion. For proper operation,

the input must be externally AC-coupled. The offset

correction circuit has been optimized for the Fibre

Channel character set, disparity rules, and 8b/10b data

encoding. This dictates an average data input mark

density of 50% and a maximum run length of five con-

secutive identical digits (CID) or bits.

CML Output Buffer

The MAX3274 CML outputs (Figure 4) provide high toler-

ance to impedance mismatches and inductive connec-

tors. The output current is approximately 24mA. The

squelch function is enabled when SQUELCH is set to a

tion holds OUT+ and OUT- at a static voltage when the

input signal level drops below the loss-of-signal thresh-

old. The output buffer can be AC- or DC-coupled to the

load. For DC operation, the load must be terminated to

Design Procedure

Programming the LOS Assert Threshold

peak differential input assert level.

Selecting the AC-Coupling Capacitors

deterministic jitter. Lowering the low-frequency cutoff

reduces deterministic jitter. The low-frequency cutoff

can be determined by:

0.1µF is recommended.

Applications Information

Optical Hysteresis

In an optical receiver, the electrical power change at

the limiting amplifier is 2 times the optical power

change. For example, if a receiver’s optical input power

(

χ) increases by a factor of 2, and the preamplifier is

linear, then the voltage input to the limiting amplifier

also increases by a factor of 2. The optical power

change is 10log (2

χ/χ) = 10log(2) = 3dB. At the limiting

amplifier, the electrical power change is:

The typical voltage hysteresis for the MAX3274 is 6dB.

This provides an optical hysteresis of 3dB.

10

2

10

2

20

2

6

2

2

2

log

/

/

log

log

VR

VR

dB

IN

IN

IN

IN

()

=

f

CR

R

C

LS

=

××

+

()

1

2

π

Dual-Rate Fibre Channel Limiting Amplifier

_______________________________________________________________________________________

7

50

LOS, LOS

OUTPUTS

50

LOS RESPONSE TIME

Figure 1. LOS Response Time