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TMP125AIDBVRG4 Datasheet(PDF) 6 Page - Texas Instruments |
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TMP125AIDBVRG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 10 page TMP125 SBOS323 − DECEMBER 2004 www.ti.com 6 0.25s 0.5s 50 µA(active) 20 µA(idle) Figure 2. Conversion Time and Period Timing Diagrams The TMP125 is SPI-compatible. Figure 3 describes the output data of the TMP125. Figure 4, Figure 5, and Figure 6 describe the various timing requirements, with parameters defined in Table 3. PARAMETER MIN MAX UNITS SCK Period t1 100 ns Data In to Rising Edge SCK Setup Time t2 20 ns SCK Falling Edge to Output Data Delay t3 30 ns SCK Rising Edge to Input Data Hold Time t4 20 ns CS to Rising Edge SCK Set-Up Time t5 40 ns CS to Output Data Delay t6 30 ns CS Rising Edge to Output High Impedance t7 30 ns Table 3. Timing Description SO SCK CS T0 T0 T0 T0 T0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Leading Zero SI Don’t Care Don’t Care Power Down Figure 3. Data READ SCK CS SO t 4 t 2 t 4 t 2 SCK CS SO Figure 4. Input Data Timing Diagram |
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