ZL10037

Data Sheet

10

Zarlink Semiconductor Inc.

The R[3:0] bits select the Reference Divider divide ratio. The ratio selected is not a simple binary power-of-two

value but through a lookup table, see Table 7- PLL Reference Divider Ratios.

This register controls test modes within the PLL. This should be programmed with the default settings.

2.2

RF Control Register

A single register controls RF programmability.

R3

R2

R1

R0

Division

Ratio

0

0002

0

0014

0

0108

0

011

16

0

100

32

01

0

1

64

0

110

128

0

111

256

1

0003

1

0015

1

010

10

1

011

20

1

100

40

11

0

1

80

1

110

160

1

111

320

Table 7 - PLL Reference Divider Ratios

Bit Field

Name

Default

Type

Description

7:0

-

0X40

R/W

Test Modes

Table 8 - Register 3

Bit Field

Name

Default

Type

Description

7

-

-

R

Test Modes

6:2

-

11011

R/W

Test Modes

1

LEN

1

R/W

Bypass Enable

0

RFG

0

R/W

RF Gain Adjust

Table 9 - Register 4