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KM736V689A Datasheet(PDF) 2 Page - Samsung semiconductor |
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KM736V689A Datasheet(HTML) 2 Page - Samsung semiconductor |
2 / 15 page PRELIMINARY KM736V689A 64Kx36 Synchronous SRAM - 2 - Rev 2.0 December 1998 WEc WEd 64Kx36-Bit Synchronous Pipelined Burst SRAM The KM736V689A is a 2,359,296-bit Synchronous Static Ran- dom Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K words of 36bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applica- tions; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is per- formed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status pro- cessor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system ′s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by cur- rent regardless of CLK. The KM736V689A is fabricated using SAMSUNG ′s high perfor- mance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to mini- mize ground bounce. GENERAL DESCRIPTION FEATURES LOGIC BLOCK DIAGRAM • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V Tolerant Inputs Except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Contention ; 2 cycle Enable, 1 cycle Disable. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • TTL-Level Three-State Output. • 100-TQFP-1420A CLK LBO ADV ADSC ADSP CS1 CS2 CS2 GW BW WEa WEb OE ZZ DQa0 ~ DQd7 BURST CONTROL LOGIC BURST 64Kx36 ADDRESS CONTROL OUTPUT DATA-IN ADDRESS COUNTER MEMORY ARRAY REGISTER REGISTER BUFFER LOGIC A ′0~A′1 A0~A1 A2~A15 A0~A15 REGISTER FAST ACCESS TIMES PARAMETER Symbol -44 -50 -55 -60 -67 -72 Unit Cycle Time tCYC 4.4 5.0 5.4 6.0 6.7 7.2 ns Clock Access Time tCD 3.1 3.1 3.1 3.5 3.8 4.0 ns Output Enable Access Time tOE 3.1 3.1 3.1 3.5 3.8 4.0 ns DQPa ~ DQPd |
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