MTV230M64
Page 9 of 31
H/V SYNC Processor Block Diagram
6.1 Composite SYNC separation/insertion
The MTV230M64 continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and user can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC will have 8us delay compared with the original signal. The
MTV230M64 can also insert pulse to HBLANK output during composite VSYNC’s active time. The insert pulse’s
width is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The HBLANK’s insert
pulse can be disable or enable by setting “NoHins” control bit.
6.2 H/V Frequency Counter
MTV230M64 can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 14 bits
Hcounter counts the time of 64xHSYNC period, then load the result into the HCNTH/HCNTL latch. The output
value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when VSYNC/CVSYNC is
present or continuously updated when VSYNC/CVSYNC is non-present. The 12 bits Vcounter counts the time
between two VSYNC pulses, then load the result into the VCNTH/VCNTL latch. The output value will be
(62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V
counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value changes or overflow. Table 6.2.1
and table 6.2.2 shows the HCNT/VCNT value under the operations of 12MHz.
Hpol
CVpre
Vbpl
VSYNC
Digital Filter
Polarity Check &
Sync Seperator
Vpre
Present
Check
Vfreq
Vpol
Polarity Check &
Freq. Count
XOR
VBLANK
XOR
HSYNC
Digital Filter
CVSYNC
Present
Check
Hpre
Hfreq
Present Check &
Freq. Count
Hbpl
XOR
HBLANK
XOR
Composite
Pulse Insert
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