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MA828
4
Fig. 3 Asynchronous PWM generation with‘double-edged’ regular sampling as used by the MA828
t1
ALE
t4
t3
t2
t8
t10
t11
t9
t12
RD
WR
AD0-AD7
CS
LATCH ADDRESS
LATCH DATA
t15
t4
t3
t8
t10
t11
t9
t12
DS
R/W
AD0-AD7
CS
LATCH ADDRESS
LATCH DATA
t1
AS
t2
t5
t6
t7
t15
Fig. 4 Intel bus timing definitions
Fig. 5 Motorola bus timing definitions
Parameter
AS high period
Delay time, as low to DS high
DS high period
Delay time, DS low to AS high
DS low period
DS high to R/W low setup time
R/W hold time
CS setup time
CS hold time
Address setup time
Address hold time
Write data setup time
Write data hold time
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t15
t11
t12
Min.
90
40
210
40
200
10
10
20
0
30
30
110
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
ALE high period
Delay time, ALE to WR
WR low period
Delay time, WR high to ALE high
CS setup time
CS hold time
Address setup time
Address hold time
Data setup time
Data hold time
Symbol
t1
t2
t3
t4
t8
t9
t10
t15
t11
t12
Min.
70
40
200
40
20
0
30
30
100
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 1 Intel bus timings at VDD = 5V, TAMB = 125°C
Table 2 Motorola bus timings at VDD = 5V, TAMB = 125°C
1
1
2
1
1
1
2
1
RESULTING
PWM
WAVEFORM
0
0
PWM SWITCHING
INSTANTS
TRIANGLE WAVE AT
CARRIER FREQUENCY,
SAMPLING ON 1VE AND 2VE PEAKS
POWER WAVEFORM
AS READ FROM
INTERNAL ROM
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