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GD25B257D Datasheet(PDF) 53 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B257D Datasheet(HTML) 53 Page - GigaDevice Semiconductor (Beijing) Inc. |
53 / 92 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B257D 53 8.20. 32KB Block Erase (BE32 52H or 4BE32 5CH) The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-Byte address on SI CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bits is not executed. Figure 51. 32KB Block Erase Sequence Diagram (ADS=0) Figure 52.32KB Block Erase Sequence Diagram (ADS=1) Figure 53. 32KB Block Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) Command 0 1 2 3 4 5 6 7 52H CS# SCLK SI 8 9 37 38 39 MSB 2 1 0 32 Bits Address 31 30 Command 0 1 2 3 4 5 6 7 52H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24 Bits Address 23 22 Command 0 1 2 3 4 5 6 7 5CH CS# SCLK SI 8 9 37 38 39 MSB 2 1 0 32 Bits Address 31 30 |
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