IDT70V9369 datasheet(3/15 Pages) IDT

Part #	IDT70V9369

Description	HIGH-SPEED 3.3V 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

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6.42

IDT70V9369L

High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

3

Preliminary

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2.

ADS, CNTEN, CNTRST = X.

3.

OE is an asynchronous input signal.

Truth Table IRead/Write and Enable Control(1,2,3)

Pin Names

Left Port

Right Port

Names

CE0L, CE1L

CE0R, CE1R

Chip Enables(2)

R/

WL

R/

WR

Read/Write Enable

OEL

OER

Output Enable

A0L - A13L

A0R - A13R

Address

I/O0L - I/O17L

I/O0R - I/O17R

Data Input/Output

CLKL

CLKR

Clock

UBL

UBR

Upper Byte Select(1)

LBL

LBR

Lower Byte Select(1)

ADSL

ADSR

Address Strobe Enable

CNTENL

CNTENR

Counter Enable

CNTRSTL

CNTRSTR

Counter Reset

FT/PIPEL

FT/PIPER

Flow-Through / Pipeline

VDD

Power (3.3V)

VSS

Ground (0V)

5648 tbl 01

OE

CLK

CE0

CE1

UB

LB

R/

W

Upper Byte

I/O9-17

Lower Byte

I/O0-8

MODE

X

↑

H

X

High-Z

Deselected–Power Down

X

↑

X

L

X

High-Z

Deselected–Power Down

X

↑

L

H

X

High-Z

Both Bytes Deselected

X

↑

LH

L

H

L

DATAIN

High-Z

Write to Upper Byte Only

X

↑

L

HHL

L

High-Z

DATAIN

Write to Lower Byte Only

X

↑

LH

LL

L

DATAIN

Write to Both Bytes

L

↑

LH

L

H

DATAOUT

High-Z

Read Upper Byte Only

L

↑

L

H

L

H

High-Z

DATAOUT

Read Lower Byte Only

L

↑

LH

LLH

DATAOUT

Read Both Bytes

H

X

L

H

L

X

High-Z

Outputs Disabled

5648 tbl 02

NOTES:

1.

LB and UB are single buffered regardless of state of FT/PIPE.

2.

CE0 and CE1 are single buffered when FT/PIPE = VIL,

CE0 and CE1 are double buffered when FT/PIPE = VIH, i.e., the signals

take two cycles to deselect.

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