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MT9M001_DS_2.fm - Rev.C 7/05 EN

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MT9M001 - 1/2-Inch Megapixel Digital Image Sensor

Serial Bus Description

Serial Bus Description

Registers are written to and read from the MT9M001 through the two-wire serial inter-

face bus. The sensor is a two-wire serial interface slave and is controlled by the serial

clock (SCLK), which is driven by the serial interface master. Data is transferred into and

down—the serial interface protocol determines which device is allowed to pull the

Protocol

The two-wire serial interface defines several different transmission codes, as follows:

•a start bit

• the slave device eight-bit address

• a(an) (no) acknowledge bit

• an 8-bit message

•a stop bit

Sequence

A typical read or write sequence begins by the master sending a start bit. After the start

bit, the master sends the slave device's eight-bit address. The last bit of the address

determines if the request will be a read or a write, where a “0” indicates a write and a “1”

indicates a read. The slave device acknowledges its address by sending an acknowledge

bit back to the master.

If the request was a write, the master then transfers the 8-bit register address to which a

write should take place. The slave sends an acknowledge bit to indicate that the register

address has been received. The master then transfers the data eight bits at a time, with

the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit

data for its internal registers, thus requiring two 8-bit transfers to write to one register.

After 16 bits are transferred, the register address is automatically incremented, so that

the next 16 bits are written to the next register address. The master stops writing by

sending a start or stop bit.

A typical read sequence is executed as follows. First the master sends the write-mode

slave address and 8-bit register address, just as in the write request. The master then

sends a start bit and the read-mode slave address. The master then clocks out the regis-

ter data eight bits at a time. The master sends an acknowledge bit after each 8-bit trans-

fer. The register address is auto-incremented after every 16 bits is transferred. The data

transfer is stopped when the master sends a no-acknowledge bit.

Bus Idle State

The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-

ated with a start bit, and the bus is released with a stop bit. Only the master can generate

the start and stop bits.

Start Bit

The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line

is HIGH.

Stop Bit

The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line

is HIGH.