UPA901TU

ILLUSTRATION OF THE TEST CIRCUIT ASSEMBLED ON EVALUATION BOARD

C1 C2

C3

C4

C10

C9

R4

R3 C6

L1

L2

C5

C7

C8

R1

R2

C11

R5

L3

L4

GND

R : 1005 Chip resistor

L : 1005 Chip inductor

C : 1005 Chip cunductor

The dotted line are connected

with the back of substrate

Remarks

1. Substrate : 20 × 20 × 0.8 (t) mm FR-4 (4 Layer, each thickness 0.2 mm), copper

thickness 18 µm, gold flash plating

2. Back side : GND pattern

3. o : Through hole

USING THE NEC EVALUATION BOARD

SYMBOL

VALUES

SYMBOL

VALUES

R1

680 Ω

C2

0.5 pF

R2

10 Ω

C3

0.5 pF

R3

10 Ω

C4

1.0 pF

R4

10 Ω

C5

0.75 pF

R5

10 Ω

C6

1.0 pF

L1

100 nH

C7

1.0 pF

L2

5.6 nH

C8

1.0 pF

L3

5.6 nH

C9

1.0 pF

L4

12 nH

C10

10 nF

C1

0.75 pF

C11

10 nF