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SP8480AS Datasheet(PDF) 6 Page - Sipex Corporation |
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SP8480AS Datasheet(HTML) 6 Page - Sipex Corporation |
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6 / 12 page  294 latch the 8 MSB’s and 4 LSB’s of output data on the 8-bit wide output data bus. The conversion cycle is started when R/C is brought low and must be held low for a mini- mum of 50ns. The R/C signal will also cause the output latches to be in a tri-state mode when low. Approximately 200ns after R/C is low, STA- TUS will change from low to high. This output signal will stay high while the SP8480 is per- forming a conversion. Valid data will be latched to the output bus, through internal control, 500ns prior to the STATUS line transitioning from a high to low. Reading the Data Please refer to Figure 5. To read data from the SP8480, the R/C and A 0 control lines are used. R/C must be high a minimum of 50ns prior to reading the data to allow time for the output latches to come out of the high impedance tri-state mode. A 0 is used to access the data. The first 8 MSBs will be on pins 26 through 19, with pin 26 being the MSB. The remaining 4 LSBs will be on pins 23 through 26 with pin 23 being the LSB. When A 0 is switched from one state to the next, there is a 50ns output latch propagation delay between the MSBs and LSBs being present on the output pins. CALIBRATION The calibration procedure for the SP8480 con- sists of adjusting the most negative input voltage (0V) to the ideal output code for offset adjust- ment, and then adjusting the most positive input voltage (5.0V) to its ideal output code for gain adjustment. SP8480 GAIN ADJUST 125K Ω +15V 10K Ω ±0.3% Trim Range 5 19K Ω Center pot for zero correction Figure 2. Gain Adjust Offset Adjustment The offset adjustment must be completed first. Please refer to Figure 1. Apply an input voltage of 0.5LSB or 610 µV to any multiplexer input. Adjust the offset potentiometer so that the output code fluctuates evenly between 000…000 and 000…001. It is only necessary to observe the lower eight LSB’s during this procedure. Gain Adjustment With the offset adjusted, the gain error can now be trimmed to zero (see Figure 2). The ideal input voltage corresponding to 1.5 LSB’s below the nominal full scale input value, or +4.988V, is applied to any multiplexer input. The gain poten- tiometer is adjusted so that the output code alternates evenly between 111…111 and 111…110. Again, only the lower eight LSB’s need be observed during this procedure. With the above adjustment made, the converter is now calibrated. SP8480 OFFSET ADJUST 100K Ω +15V 5K Ω –1.5mV to +3mV 4 Figure 1. Offset Adjust |
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