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KS57P21632 Datasheet(PDF) 2 Page - Samsung semiconductor |
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KS57P21632 Datasheet(HTML) 2 Page - Samsung semiconductor |
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2 / 27 page  PRODUCT OVERVIEW KS57C21632/P21632 1-2 FEATURES Memory • 768 × 4-bit RAM (excluding LCD display RAM) • 32,768 × 8-bit ROM 12 I/O Pins • I/O: 12 pins LCD Controller/Driver • 56 segments and 16 common terminals (8, 12 and 16 common selectable) • Capacitor bias for LCD output. • Voltage booster and regulator • All dots can be switched on/off 8-bit Basic Timer • 4 interval timer functions • Watch-dog timer One 16-bit Timer/Counter 1 • Programmable 16-bit timer • Arbitrary clock output (TCLO1) • Inverted clock output (TCLO1) • Configurable two 8-bit timer/counters Watch Timer • Time interval generation: 0.5 s, 3.9 ms at 32768 Hz • Four frequency outputs to BUZ pin and BUZ pin • Clock source generation for LCD Battery Level Detector • Programmable low voltage detector • One criteria voltage (2.4 V) Interrupts • Three Internal vectored interrupt • Four external vectored interrupts • Two quasi-interrupts Memory-Mapped I/O Structure • Data memory bank 15 Power-Down Modes • Idle mode (only CPU clock stops) • Stop mode (main system oscillation stops) • Subsystem clock stop mode Oscillation Sources • Crystal, ceramic, or RC for main system clock • Crystal oscillator for subsystem clock • Main system clock frequency: 0.4-4.19 MHz • Subsystem clock frequency: 32.768 kHz • CPU clock divider circuit (by 4, 8, or 64) Instruction Execution Times • 0.95, 1.91, 15.3 µs at 4.19 MHz (main) • 122 µs at 32.768 kHz (subsystem) Operating Temperature • – 40 °C to 85 °C Operating Voltage Range • 2.2 V to 3.4 V (0.4 MHz to 4.19 MHz) Package Type • 100-pin QFP or pellet |
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