DDR SDRAM

DDR SDRAM 256Mb F-die (x8, x16)

Rev. 1.1 August. 2003

• 200MHz Clock, 400Mbps data rate.

• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• MRS cycle with address key programs

-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

• Data I/O transactions on both edges of data strobe

• Edge aligned data output, center aligned data input

• LDM,UDM for write masking only (x16)

• Auto & Self refresh

• 7.8us refresh interval(8K/64ms refresh)

• Maximum burst refresh cycle : 8

Ordering Information

Part No.

Org.

Max Freq.

Interface

Package

K4H560838F-UCCC

32M x 8

CC(DDR400@CL=3)

SSTL2

66pin TSOP II

K4H560838F-UCC4

C4(DDR400@CL=3)

K4H561638F-UCCC

16M x 16

CC(DDR400@CL=3)

SSTL2

66pin TSOP II

K4H561638F-UCC4

C4(DDR400@CL=3)

Key Features

*CL : CAS Latency

Operating Frequencies

- CC(DDR400@CL=3)

- C4(DDR400@CL=3)

Speed @CL3

200MHz

200MHz

CL-tRCD-tRP

3 - 3 - 3

3 - 4 - 4