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TMS320VC5410AZGU16 Datasheet(PDF) 7 Page - Texas Instruments |
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TMS320VC5410AZGU16 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 100 page www.ti.com TMS320VC5410A Fixed-Point Digital Signal Processor SPRS139G – NOVEMBER 2000 – REVISED JANUARY 2005 List of Tables 2-1 Terminal Assignments ........................................................................................................... 11 2-2 Signal Descriptions ............................................................................................................... 13 3-1 Standard On-Chip ROM Layout ................................................................................................ 19 3-2 Processor Mode Status Register (PMST) Field Descriptions ............................................................... 22 3-3 Software Wait-State Register (SWWSR) Field Descriptions ................................................................ 23 3-4 Software Wait-State Control Register (SWCR) Field Descriptions ......................................................... 24 3-5 Bank-Switching Control Register (BSCR) Field Descriptions ............................................................... 25 3-6 Bus Holder Control Bits .......................................................................................................... 26 3-7 Sample Rate Generator Clock Source Selection ............................................................................. 30 3-8 Receive Channel Enable Registers for Partitions A to H Field Descriptions .............................................. 31 3-9 Transmit Channel Enable Registers for Partitions A to H Field Descriptions ............................................. 31 3-10 Clock Mode Settings at Reset ................................................................................................... 33 3-11 DMD Section of the DMMCRn Register ........................................................................................ 38 3-12 DMA Channel Enable Control Register (DMCECTL) Field Descriptions .................................................. 39 3-13 DMA Reload Register Selection ................................................................................................ 42 3-14 DMA Interrupts .................................................................................................................... 43 3-15 DMA Synchronization Events .................................................................................................... 44 3-16 DMA Channel Interrupt Selection ............................................................................................... 44 3-17 CPU Memory-Mapped Registers ................................................................................................ 47 3-18 Peripheral Memory-Mapped Registers for Each DSP Subsystem ......................................................... 48 3-19 McBSP Control Registers and Subaddresses ................................................................................. 49 3-20 DMA Subbank Addressed Registers ........................................................................................... 50 3-21 Interrupt Locations and Priorities ................................................................................................ 52 5-1 Input Clock Frequency Characteristics ......................................................................................... 58 5-2 Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options ........................................ 59 5-3 Divide-By-2 and Divide-By-4 Clock Options Timing Requirements ........................................................ 59 5-4 Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics .................................................... 59 5-5 Multiply-By-N Clock Option Timing Requirements ............................................................................ 61 5-6 Multiply-By-N Clock Option Switching Characteristics ....................................................................... 61 5-7 Memory Read Timing Requirements ........................................................................................... 62 5-8 Memory Read Switching Characteristics ....................................................................................... 62 5-9 Memory Write Switching Characteristics ....................................................................................... 65 5-10 I/O Read Timing Requirements ................................................................................................. 67 5-11 I/O Read Switching Characteristics ............................................................................................. 67 5-12 I/O Write Switching Characteristics ............................................................................................. 69 5-13 Ready Timing Requirements for Externally Generated Wait States ....................................................... 70 5-14 Ready Switching Characteristics for Externally Generated Wait States ................................................... 70 5-15 HOLD and HOLDA Timing Requirements ..................................................................................... 73 5-16 HOLD and HOLDA Switching Characteristics ................................................................................. 73 List of Tables 7 |
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