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TMP95C061 Datasheet(PDF) 11 Page - Toshiba Semiconductor |
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TMP95C061 Datasheet(HTML) 11 Page - Toshiba Semiconductor |
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11 / 192 page  TOSHIBA CORPORATION 11 TMP95C061 3.3.1 General-Purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows: (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority (which is fixed as follows: the smaller the vector value, the higher the priority), then clears the interrupt request. (2) The CPU pushes the program counter and the status register to the system stack area (area indicated by the system mode stack pointer(XSP)). (3) The CPU sets a value in the CPU interrupt mask regis- ter <IFF2 to 0> that is higher by 1 than the value of the accepted interrupt level. However, if the value is 7, 7 is set without an increment. (4) The CPU increments the INTNEST (Interrupt Nesting Counter). (5) The CPU jumps to address FFFF00H + interrupt vec- tor, then starts the interrupt processing routine. To return to the main routine after completion of the inter- rupt processing, the RETI instruction is usually used. Executing this instruction restores the contents of the program counter and the status registers and decements the INTNEST (Inter- rupt Nesting Counter). Though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. A priority can be set for each source of maskable inter- rupts. The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register <IFF2 to 0>. The CPU mask register <IFF2 to 0> is set to a value higher by 1 than the priority of the accepted interrupt. Thus, if an inter- rupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest. If an interrupt generated while the CPU is performing pro- cesses (1) to (5) for an earlier interrupt, the new interrupt is sampled immediately after the start instruction of the interrupt processing is executed. Setting DI as the start instruction dis- ables maskable interrupt nesting. (Note: With the 900 and 900/L, an interrupt is sampled before the start instruction is executed.) Resetting initializes the CPU mask registers <IFF2 to 0> to 7; therefore, maskable interrupts are disabled. The addresses 0FFFF00H to 0FFFFFFH (256 bytes) of the TMP95C061 are assigned for interrupt processing entry area. Bus Width of Stack Area Bus Width Interrupt Vector Area Interrupt Processing State Number MAX mode Min mode 8 bit 8 bit 23 24 16 bit 24 20 16 bit 8 bit 22 20 16 bit 18 16 |
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