W946432AD datasheet(6/40 Pages) WINBOND

Part #	W946432AD

Description	512K X 4 BANKS X 32 BITS DDR SDRAM

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Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

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W946432AD

AC OPERATING CONDITIONS

(0°C

≤ TA ≤ 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH

(AC)

VREF +

0.35

V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

VIL

(AC)

VREF -

0.35

V

Input Differential Voltage, CK and CK inputs

VID

(AC)

0.7

VDDQ + 0.6

V

5

Input Crossing Point Voltage, CK and CK inputs

VIX

(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

7

IDD SPECIFICATIONS AND CONDITIONS

(0°C

≤ TA ≤ 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V)

MAX

SYMBOL

UNITS

NOTES

OPERATING CURRENT: One Bank; Active-Precharge;

tRC = tRC MI

N; tCK = tCK MIN; DQ, DM and DQS inputs changing twice per

clock cyle; address and control inputs changing once per clock cycle

IDD0

TBD

mA

OPERATING CURRENT: One Bank; Active-Read-Precharge;

Burst = 2; tRC = tRC MI

N; CL = 3 ; tCK = tCK MIN; IOUT= 0 mA;

Address and control inputs changing once per clock cycle

IDD1

TBD

mA

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;

power-down mode; CKE

≤ VIL (MAX); tCK = tCK MIN

IDD2P

TBD

mA

IDLE STANDBY CURRENT: CS

≥ VIH (MIN); All banks idle;

CKE

≥ VIH (MIN); tCK = tCK MIN; Address and other control inputs

changing once per clock cycle

IDD2N

TBD

mA

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;

power-down mode; CKE

≤ VIL (MAX); tCK = tCK MIN

IDD3P

TBD

mA

ACTIVE STANDBY CURRENT: CS

≥ VIH (MIN); CKE ≥ VIH (MIN);

One bank; Active-Precharge; tRC = tRAS MA

X; tCK = tCK MIN; DQ,

DM and DQS inputs changing twice per clock cycle; address and

other control inputs changing once per clock cycle

IDD3N

TBD

mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

One bank active; Address and control inputs changing once per clock

cycle; CL = 3 ; tCK = tCK MIN; IOUT = 0 mA

IDD4R

TBD

mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

One bank active; Address and control inputs changing once per clock

cycle; CL = 3 ; tCK = tCK MIN; DQ, DM and DQS inputs changing

twice per clock cycle

IDD4W

TBD

mA

AUTO REFRESH CURRENT: tRC = tRFC (MI

N)

IDD5

TBD

mA

SELF REFRESH CURRENT: CKE

≤ 0.2V

IDD6

TBD

mA

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