SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

SDRAM 256Mb E-die (x4, x8, x16)

PIN CONFIGURATION (Top view)

N.C

N.C

DQ0

N.C

N.C

N.C

DQ1

N.C

N.C

WE

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

N.C

N.C

DQ3

N.C

N.C

N.C

DQ2

N.C

N.C/RFU

DQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

54Pin TSOP

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

CS

Chip select

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

Address

Row/column addresses are multiplexed on the same pins.

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE

Write enable

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM

Data input/output mask

Blocks data input when DQM active.

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power supply/ground

Power and ground for the input buffers and the core logic.

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No connection

/reserved for future use

This pin is recommended to be left No Connection on the device.

DQ0

N.C

DQ1

N.C

DQ2

N.C

DQ3

N.C

N.C

WE

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

DQ7

N.C

DQ6

N.C

DQ5

N.C

DQ4

N.C

N.C/RFU

DQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

LDQM

WE

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

N.C/RFU

UDQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

x16

x8

x4

x16

x8

x4