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TLV320AIC32IRHBRG4 Datasheet(PDF) 10 Page - Burr-Brown (TI) |
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TLV320AIC32IRHBRG4 Datasheet(HTML) 10 Page - Burr-Brown (TI) |
10 / 72 page www.ti.com th(WS) ts(WS) ts(DI) th(DI) td(DO−BCLK) WCLK BCLK SDOUT SDIN tH(BCLK) tL(BCLK) tP(BCLK) ts(WS) th(WS) TIMING CHARACTERISTICS (1) TLV320AIC32 SLAS479A – AUGUST 2005 – REVISED SEPTEMBER 2005 Figure 5. DSP Timing in Slave Mode All specifications typical at 25 °C, DVDD = 1.8 V IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX tH (BCLK) BCLK high period 70 35 ns tL (BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 8 ns th(WS) ADWS/WCLK hold time 10 8 ns td BCLK to DOUT delay time 50 20 ns (DO-BCLK) ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns (1) All timing specifications are measured at characterization but not tested at final test. 10 |
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