M368L1624DTM-LCC datasheet(8/22 Pages) SAMSUNG

Part #	M368L1624DTM-LCC

Description	184pin Unbuffered Module based on 256Mb D-die 64/72-bit Non ECC/ECC

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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DDR SDRAM

Rev. 1.2 May. 2003

128MB, 256MB, 512MB Unbuffered DIMM

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DM

I/O 7

I/O 6

I/O 1

I/O 0

D0

DM0

DM

D8

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DM

I/O 7

I/O 6

I/O 1

I/O 0

D1

DM

D9

I/O 5

I/O 4

I/O 3

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

DM1

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DM

I/O 7

I/O 6

I/O 1

I/O 0

D2

DM

D10

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM2

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DM

I/O 7

I/O 6

I/O 1

I/O 0

D3

DM

D11

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM3

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DM

I/O 7

I/O 6

I/O 1

I/O 0

D4

DM4

DM

D12

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DM

I/O 7

I/O 6

I/O 1

I/O 0

D5

DM

D13

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DM

I/O 7

I/O 6

I/O 1

I/O 0

D6

DM

D14

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DM

I/O 7

I/O 6

I/O 1

I/O 0

D7

DM

D15

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM7

CS0

CS1

CS

DQS0

DQS

DQS4

DQS1

DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6

DQS6

DQS7

DQ15

I/O 2

I/O 5

DQS

512MB, 64M x 64 Non ECC Module (M368L6423DTM) (Populated as 2 bank of x8 DDR SDRAM Module)

Functional Block Diagram

Clock Wiring

CK0/CK0

Clock

Input

SDRAMs

CK1/CK1

4 SDRAMs

6 SDRAMs

CK2/CK2

A0

Serial PD

A1

A2

SA0

SA1

SA2

SCL

SDA

WP

VSS

D0 - D15

VDD/VDDQ

D0 - D15

VREF

VDDSPD

SPD

Notes :

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors: 3.0 Ohms +

5%

A0 - A12

A0-A12 : DDR SDRAMs D0 - D15

RAS

RAS : DDR SDRAMs D0 - D15

CAS

CAS : DDR SDRAMs D0 - D15

WE

WE : DDR SDRAMs D0 - D15

CKE1

CKE : DDR SDRAMs D8 - D15

BA0 - BA1

BA0-BA1 : DDR SDRAMs D0 - D15

CKE0

CKE : DDR SDRAMs D0 - D7

*Clock Net Wiring

Card

Edge

D3/D0/D5

D4/D1/D6

Cap/D2/D7

Cap/D8/D13

D11/D9/D14

D12/D10/D15

R=120

Ω

CK0/1/2

Cap will replace DRAM

*If four DRAMs are loaded,

*

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