NCP1575

http://onsemi.com

10

APPLICATION INFORMATION

THEORY OF OPERATION

The NCP1575 is a simple, synchronous, fixed−frequency,

the ESR of the output capacitors. This ramp is proportional

to the ac current through the main inductor and is offset by

the dc output voltage. This control scheme inherently

compensates for variation in either line or load conditions,

since the ramp signal is generated from the output voltage

such as voltage mode control, which generates an artificial

ramp, and current mode control, which generates a ramp

using the inductor current.

COMP

Reference

Voltage

+

+

PWM

RAMP

Error

Amplifier

Error

Signal

Output

Voltage

GATE(H)

GATE(L)

−

−

Slope

Compensation

output voltage generates both the error signal and the ramp

signal. Since the ramp signal is simply the output voltage, it

is affected by any change in the output, regardless of the

origin of that change. The ramp signal also contains the DC

portion of the output voltage, allowing the control circuit to

drive the main switch from 0% to 100% duty cycle as

required.

A variation in line voltage changes the current ramp in the

the duty cycle. Since any variation in inductor current

control scheme offers the same advantages in line transient

response.

A variation in load current will affect the output voltage,

modifying the ramp signal. A load step immediately changes

the state of the comparator output, which controls the main

switch. The comparator response time and the transition

speed of the main switch determine the load transient

response. Unlike traditional control methods, the reaction

time to the output load step is not related to the crossover

frequency of the error signal loop.

The error signal loop can have a low crossover frequency,

since the transient response is handled by the ramp signal

loop. The main purpose of this ‘slow’ feedback loop is to

provide dc accuracy. Noise immunity is significantly

improved, since the error amplifier bandwidth can be rolled

off at a low frequency. Enhanced noise immunity improves

remote sensing of the output voltage, since the noise

associated with long feedback traces can be effectively

filtered.

Line and load regulation are drastically improved because

there are two independent control loops. A voltage mode

controller relies on the change in the error signal to

compensate for a deviation in either line or load voltage.

This change in the error signal causes the output voltage to

change corresponding to the gain of the error amplifier,

which is normally specified as line and load regulation. A

current mode controller maintains a fixed error signal during

line transients, since the slope of the ramp signal changes in

this case. However, regulation of load transients still requires

maintains a fixed error signal for both line and load variation,

since the ramp signal is affected by both line and load.

The stringent load transient requirements of modern

microprocessors require the output capacitors to have very

low ESR. The resulting shallow slope in the output ripple can

lead to pulse width jitter and variation caused by both random

and synchronous noise. A ramp waveform generated in the

oscillator is added to the ramp signal from the output voltage

to provide the proper voltage ramp at the beginning of each

switching cycle. This slope compensation increases the noise

immunity, particularly at duty cycles above 50%.

Startup

The NCP1575 features a programmable soft−start

function, which is implemented through the error amplifier

and the external compensation capacitor. This feature

prevents stress to the power components and limits output

voltage overshoot during startup. As power is applied to the

regulator, the NCP1575 undervoltage lockout circuit (UVL)

holds the GATE(H) output low and the GATE(L) output

function of 1.0 V improves noise immunity. The

compensation capacitor connected to the COMP pin is

charged by a 30

mA current source. When the capacitor

voltage exceeds the 0.465 V offset of the PWM comparator,

the PWM control loop will allow switching to occur. The

upper gate driver GATE(H) is activated, turning on the upper

MOSFET. The current ramps up through the main inductor

and linearly powers the output capacitors and load. When

the regulator output voltage exceeds the COMP pin voltage

minus the 0.465 V PWM comparator offset threshold and

the artificial ramp, the PWM comparator terminates the

initial pulse.