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M5M4V64S20ATP-10L Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor |
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M5M4V64S20ATP-10L Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor |
2 / 51 page MITSUBISHI LSIs MITSUBISHI ELECTRIC M5M4V64S20ATP-8A,-8L,-8, -10L, -10 SDRAM (Rev.1.3) 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM Mar98 BLOCK DIAGRAM Address Buffer A0-11 BA0,1 Control Signal Buffer /CS /RAS /CAS /WE DQM CLK CKE Clock Buffer Memory Array Bank #0 Control Circuitry I/O Buffer DQ0-3 Mode Register Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Type Designation Code M 5M 4 V 64 S 2 0 A TP - 8 Access Item Package Type TP: TSOP(II) Process Generation Function 0: Random Column, 1: 2N-rule Organization 2n 2: x4, 3: x8, 4: x16 Synchronous DRAM Density 64:64M bits Interface S: SSTL, V:LVTTL Memory Style (DRAM) Use, Recommended Operating Conditions, etc Mitsubishi Main Designation This rule is applied to only Synchronous DRAM family. 2 |
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