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M5M467805BTP-6 Datasheet(PDF) 11 Page - Mitsubishi Electric Semiconductor |
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M5M467805BTP-6 Datasheet(HTML) 11 Page - Mitsubishi Electric Semiconductor |
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11 / 39 page  MITSUBISHI ELECTRIC Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs (Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S 11 Write Cycle (Early Write and Delayed Write) Parameter Symbol Read-Write and Read-Modify-Write Cycles Limits Parameter Symbol Limits Unit M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S OE hold time after W low Read write/read modify write cycle time RAS low pulse width CAS low pulse width tRWC tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low (Note23) (Note24) 44 44 0 32 77 47 38 109 38 70 0 28 65 40 tCWD tRWD tAWD Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low (Note24) (Note24) 10000 10000 10000 10000 75 133 89 82 ns ns ns ns ns ns ns ns ns Min Max Min Max ns 15 13 tOEH Write cycle time RAS low pulse width CAS low pulse width tWC 8 tRAS tCAS tCSH tRSH tWCS CAS hold time after RAS low Write setup time before CAS low Write hold time after CAS low (Note 24) tWCH tCWL 0 tRWL tWP tDS RAS hold time after CAS low CAS hold time after W low 10000 10000 10000 10000 84 50 8 35 13 8 0 10 0 104 60 10 40 15 10 0 8 10 tDH RAS hold time after W low Data setup time before CAS low or W low Data hold time after CAS low or W low Write pulse width ns ns ns ns ns ns ns ns Unit Min Max Min Max ns ns ns ns 8 10 8 10 Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi- nate. ≥ ≥ ≥ ≥ ≥ M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S |
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