M5M4V64S40ATP-10L datasheet(3/51 Pages) MITSUBISHI

Part #	M5M4V64S40ATP-10L

Description	64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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MITSUBISHI LSIs

MITSUBISHI ELECTRIC

SDRAM (Rev.1.3)

M5M4V64S40ATP-8A,-8L,-8, -10L, -10

64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

Mar'98

PIN FUNCTION

CLK

Input

Master Clock: All other inputs are referenced to the rising edge of CLK.

CKE

Input

Clock Enable: CKE controls internal clock. When CKE is low, internal clock

for the following cycle is ceased. CKE is also used to select auto / self

refresh. After self refresh mode is started, CKE becomes asynchronous

input. Self refresh is maintained as long as CKE is low.

/CS

Input

Chip Select: When /CS is high, any command means No Operation.

/RAS, /CAS, /WE

Input

Combination of /RAS, /CAS, /WE defines basic commands.

A0-11

Input

A0-11 specify the Row / Column Address in conjunction with BA0,1. The

Row Address is specified by A0-11. The Column Address is specified by

A0-7 . A10 is also used to indicate precharge option. When

A10 is high at a read / write command, an auto precharge is performed.

When A10 is high at a precharge command, all banks are precharged.

BA0,1

Input

Bank Address: BA0,1 specifies one of four banks to which a command is

applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.

DQ0-15

Input / Output

Data In and Data out are referenced to the rising edge of CLK.

DQMU/L

Input

Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the

current cycle is masked. When DQMU/L is high in burst read,

Dout is disabled at the next but one cycle.

Vdd, Vss

Power Supply

Power Supply for the memory array and peripheral circuitry.

VddQ, VssQ

Power Supply

VddQ and VssQ are supplied to the Output Buffers only.

3

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