Integrated Circuit Solution Inc.

1

SR001-B

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.

We assume no responsibility for any errors

which may appear in this publication.

© Copyright 2000, Integrated Circuit Solution Inc.

FEATURES

•

High-speed access time: 15, 20, 25 ns

•

Automatic power-down when chip is

deselected

•

CMOS low power operation

— 450 mW (typical) operating

— 250 µW (typical) standby

•

TTL compatible interface levels

•

Single 5V power supply

•

Fully static operation: no clock or refresh

required

•

Three state outputs

•

Two Chip Enables (

CE1 and CE2) for

simple memory expansion

IS61C64AH

8K x 8 HIGH-SPEED CMOS STATIC RAM

DESCRIPTION

The

ICSI

IS61C64AH is a very high-speed, low power,

8192-word by 8-bit static RAM. It is fabricated using

ICSI

's

high-performance CMOS technology. This highly reliable pro-

cess coupled with innovative circuit design techniques, yields

access times as fast as 15 ns with low power consumption.

When

CE1 is HIGH or CE2 is LOW (deselected), the device

assumes a standby mode at which the power dissipation can

be reduced down to 250 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using two Chip Enable

inputs,

CE1 and CE2. The active LOW Write Enable (WE)

controls both writing and reading of the memory.

The

IS61C64AH is packaged in the JEDEC standard 28-pin,

300mil SOJ and 330mil SOP.

FUNCTIONAL BLOCK DIAGRAM

A0-A12

CE1

OE

WE

256 X 256

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

CE2