CHIP SELECTION
Multilayer capacitors (MLC) are categorized by dielectric
performance with temperature, or “temperature coefficient”,
as these devices vary in behavior over temperature. The choice
of component is thus largely determined by the temperature
stability required of the device, i.e. type of dielectric, and the size
necessary for a given capacitance and voltage rating. The following
items are pertinent to chip selection:
DIELECTRIC TYPE
COG: Ultra stable Class I dielectric, with negligible dependence of
electrical properties on temperature, voltage, frequency and time.
Used in circuitry requiring very stable performance.
X7R: Stable Class II dielectric, with predictable change in properties
with temperature, voltage, frequency and time. Used as blocking,
de-coupling, bypassing and frequency discriminating elements. This
dielectric is ferroelectric, and provides higher capacitance than Class I
Z5U/Y5V: General purpose Class III dielectrics with higher dielectric
constant and greater variation of properties with temperature and
test conditions. Very high capacitance per unit volume is attainable for
general purpose applications where stability is not important.
CAPACITOR SIZE
Size selection is based primarily on capacitance value and voltage rat-
ing. Smaller units are generally less expensive; 0805 is the most eco-
nomical size. Because mass affects the thermal shock behavior of
chips, size selection must consider the soldering method used to
attach the chip to the board. Sizes 1812 and smaller can be wave,
vapor phase or reflow soldered. Larger units require reflow soldering.
TERMINATION MATERIAL
Nickel barrier termination, with exceptional solder leach resistance is
recommended for all applications involving solder. Silver palladium
termination is required for epoxy attachment, also for solder reflow
below 230°C . Silver termination, which is most ductile, yet leaches
readily in solder, is often preferred for units to be leaded, to minimize
thermal cycle stresses.
PACKAGING
Units are available in bulk, reeled or in waffle pack. Bar coding is
optional.
6
ATTACHMENT METHODS
Bonding of capacitors to substrates can be categorized into two
methods, those involving solder, which are prevalent, and those
using other materials, such as epoxies and thermo-compression or
ultrasonic bonding with wire.
SOLDERING
Soldering methods commonly used in the industry and recom-
mended are Reflow Soldering, Wave Soldering, and to a lesser
extent, Vapor Phase Soldering. All these methods involve thermal
cycling of the components and therefore the rate of heating and
cooling must be controlled to preclude thermal shocking of the
devices. In general, rates which do not exceed 100°C per minute
and a
∆T spike of 100°C maximum for any soldering process is
advisable. Other precautions include post soldering handling,
primarily avoidance of rapid cooling with contact with heat sinks,
such as conveyors or cleaning solutions.
Large chips are more prone to thermal shock as their greater bulk
will result in sharper thermal gradients within the device during
thermal cycling. Units larger than 1812 experience excessive stress
if processed through the fast cycles typical of solder wave or vapor
phase operations. Solder reflow is most applicable to the larger
chips as the rates of heating and cooling can be slowed within safe
limits.
Attachment using a soldering iron requires extra care, particularly
with large components, as thermal gradients are not easily
controlled and may cause cracking of the chip. Precautions include
preheating of the assembly to within 100°C of the solder flow
temperature, the use of a fine tip iron which does not exceed 30
watts, and limitation of contact of the iron to the circuit pad areas
only.
BONDING
Hybrid assembly using conductive epoxy or wire bonding requires
the use of silver palladium or gold terminations. Nickel barrier
termination is not practical in these applications, as an increase in
ESR results.
CLEANING
Chip capacitors can withstand common agents such as
water, alcohol and degreaser solvents used for clean-
ing boards. Ascertain that no flux residues are left
on the chip surfaces as these diminish
electrical performance.
APPLICA TION
NOTES
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