Electronic Components Datasheet Search |
|
IDTCSPU877ANLG Datasheet(PDF) 6 Page - Integrated Device Technology |
|
IDTCSPU877ANLG Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 13 page 6 COMMERCIALTEMPERATURERANGE IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TIMING REQUIREMENTS Symbol Parameter Min. Max. Unit fCLK Operating Clock Frequency(1,2) 125 270 MHz Application Clock Frequency(1,3) 160 270 MHz tDC Input Clock Duty Cycle 40 60 % tL StabilizationTime(4) 15 µs NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic LOW state, enters the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle. AC ELECTRICAL CHARACTERISTICS(1) Symbol Description Test Conditions Min. Typ.(2) Max. Unit tPLH(2) LOW to HIGH Level Propagation Delay Time AVDD = GND, OE = H, OS = L, TBD ns CLK to any output tPHL(2) HIGH to LOW Level Propagation Delay Time AVDD = GND, OE = H, OS = L, TBD ns CLK to any output tJIT(CC+) Jitter(cycle-to-cycle) 166/200/266MHz 0 40 ps tJIT(CC-) 0 -40 tJIT(PER)(3) Jitter(period) 166/200/266MHz -40 40 ps tJIT(HPER)(3) Half-PeriodJitter 166/200/266MHz -60 60 ps tSLR(O)(1,4) OutputClockSlewRate(single-ended) 166/200/266MHz (20% to 80%) 1.5 2.5 3 V/ns tSLR(I)(1,4) OutputEnable(OE) 0.5 V/ns Input Clock Slew Rate 1 2.5 4 t(∅)(5) StaticPhaseOffset 166/200/266MHz -50 50 ps t(∅)DYN DynamicPhaseOffset 166/200/266MHz -50 50 ps tSK(O) Output Skew 40 ps tEN Output Enable to any Y or Y 8ns tDIS Output Disable to any Y or Y 8ns VOX(6) ACDifferentialOutputCrosspointVoltage Differentialoutputsterminatedwith120 Ω (VDDQ/2)-0.1 (VDDQ/2)+0.1 V VID(AC) ACDifferentialInputVoltage 0.6 VDDQ+0.4 V VIX ACDifferentialInputCrosspointVoltage (VDDQ/2)-0.15 (VDDQ/2)+0.15 V The PLL on the CSPU877A will meet all the above test parameters while supporting SSC synthesizers with the following parameters: SSC ModulationFrequency 30 33 KHz SSC ClockInputFrequencyDeviation 0 -0.5 % f3dB PLLLoopBandwidth 2 MHz NOTES: 1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50 Ω equal length cables with SMA connectors on the test board. 2. Refers to transition of non-inverting output. 3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other. 4. To eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK, CLK) and feedback clock input (FBIN, FBIN) are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nominal values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 5. Static phase offset does not include jitter. 6. VOX is specified at the DDR DRAM clock input or test load. |
Similar Part No. - IDTCSPU877ANLG |
|
Similar Description - IDTCSPU877ANLG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |