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S3904-1024F Datasheet(PDF) 2 Page - Hamamatsu Corporation

Part # S3904-1024F
Description  NMOS Linear image sensor
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Manufacturer  HAMAMATSU [Hamamatsu Corporation]
Direct Link  http://www.hamamatsu.com
Logo HAMAMATSU - Hamamatsu Corporation

S3904-1024F Datasheet(HTML) 2 Page - Hamamatsu Corporation

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NMOS linear image sensor
S3901/S3904-F series
s
Shape specifications
Parameter
S3901-256F
S3901-512F
S3904-512F
S3904-1024F
Unit
Number of pixels
256
512
512
1024
-
Package length
31.75
40.6
31.75
40.6
mm
Number of pins
22
22
-
Window material
Fiber optic plate
Fiber optic plate
-
Weight
8.0
10.0
8.0
10.0
g
s
Specifications (Ta=25 °C)
S3901-F series
S3904-F series
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Pixel pitch
-
-
50
-
-
25
-
µm
Pixel height
-
-
2.5
-
-
2.5
-
mm
Spectral response range
(10 % of peak)
λ
360 to 1000
360 to 1000
nm
Peak sensitivity wavelength
λp
-
600
-
-
600
-
nm
Photodiode dark current *3
ID
-
0.2
0.6
-
0.1
0.3
pA
Photodiode capacitance *3
Cph
-
20
-
-
10
-
pF
Saturation exposure *3, *4
Esat
-
200
-
-
200
-
mlx · s
Saturation output charge *3
Qsat
-
50
-
-
25
-
pC
Photo response non-uniformity *5
PRNU
-
-
±5
-
-
±5
%
*3: Vb=2.0 V, Vφ=5.0 V
*4: 2856 K, tungsten lamp
*5: 50 % of saturation, excluding the start pixel and last pixel
s
Electrical characteristics (Ta=25 °C)
S3901-F series
S3904-F series
Parameter
Symbol
Condition
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
High Vφ1, Vφ2 (H)
4.5
5
10
4.5
5
10
V
Clock pulse (φ1, φ2)
voltage
Low Vφ1, Vφ2 (L)
0-
0.4
0
-
0.4
V
High
Vφs (H)
4.5
Vφ1
10
4.5
Vφ1
10
V
Start pulse (φst) voltage
Low
Vφs (L)
0
-
0.4
0
-
0.4
V
Video bias voltage *6
Vb
1.5
Vφ - 3.0 Vφ - 2.5
1.5
Vφ - 3.0 Vφ - 2.5
V
Saturation control gate voltage
Vscg
-
0
-
-
0
-
V
Saturation control drain voltage
Vscd
-
Vb
-
-
Vb
-
V
Clock pulse (φ1, φ2) rise / fall time *7
trφ1, trφ2
tfφ1, tfφ2
-
20
-
-
20
-
ns
Clock pulse (φ1, φ2) pulse width
tpwφ1, tpwφ2
200
-
-
200
-
-
ns
Start pulse (φst) rise / fall time
trφs, tfφs
-
20
-
-
20
-
ns
Start pulse (φst) pulse width
tpwφs
200
-
-
200
-
-
ns
Start pulse (φst) and clock pulse
(φ2) overlap
tφov
200
-
-
200
-
-
ns
Clock pulse space *7
X1, X2
trf - 20
-
-
trf - 20
-
-
ns
Data rate *8
f
0.1
-
2000
0.1
-
2000
kHz
-
120 (-256 F)
--
150 (-512 F)
-ns
Video delay time
tvd
50 % of
saturation
*8, *9
-
160 (-512 F)
--
200 (-1024 F)
-ns
-
36 (-256 F)
-
-
50 (-512 F)
-
pF
Clock pulse (φ1, φ2)
line capacitance
5 V bias
-
67 (-512 F)
-
-
100 (-1024 F)
-
pF
-
20 (-256 F)
--
24 (-512 F)
-pF
Saturation control gate (Vscg)
line capacitance
Cscg
5 V bias
-
35 (-512 F)
--
45 (-1024 F)
-pF
-
11 (-256 F)
-
-
16 (-512 F)
-
pF
Video line capacitance
CV
2 V bias
-
20 (-512 F)
-
-
30 (-1024 F)
-
pF
*6: Vφ is input pulse voltage.
*7: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more should be input
if the clock pulse rise or fall time is longer than 20 ns.
*8: Vb=2.0 V, Vφ=5.0 V
*9: Measured with C7883 driver circuit.


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