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S3904-2048Q Datasheet(PDF) 2 Page - Hamamatsu Corporation

Part # S3904-2048Q
Description  NMOS Linear image sensor
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Manufacturer  HAMAMATSU [Hamamatsu Corporation]
Direct Link  http://www.hamamatsu.com
Logo HAMAMATSU - Hamamatsu Corporation

S3904-2048Q Datasheet(HTML) 2 Page - Hamamatsu Corporation

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NMOS linear image sensor
S3901-1024Q, S3904-2048Q
s Shape specifications
Parameter
S3901-1024Q
S3904-2048Q
Unit
Number of pixels
1024
2048
-
Package length
65.0
mm
Number of pin
22
-
Window material *
3
Quartz
-
Weight
8.5
g
*3: Fiber optic plate is available.
s Specifications (Ta=25 °C)
S3901-1024Q
S3904-2048Q
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Pixel pitch
-
-
50
-
-
25
-
µm
Pixel height
-
-
2.5
-
-
2.5
-
mm
Spectral response range
(10 % of peak)
λ
200 to 1000
200 to 1000
nm
Peak sensitivity wavelength
λp
-
600
-
-
600
-
nm
Photodiode dark current *
4
ID
-
0.2
0.6
-
0.1
0.3
pA
Photodiode capacitance *
4
Cph
-
20
-
-
10
-
pF
Saturation exposure *
4, *5
Esat
-
180
-
-
180
-
mlx · s
Saturation output charge *
4
Qsat
-
50
-
-
25
-
pC
Photo response non-uniformity *
6
PRNU
-
-
±3
-
-
±3
%
*4: Vb=2.0 V, V
φ=5.0 V
*5: 2856 K, tungsten lamp
*6: 50 % of saturation, excluding the start pixel and last pixel
s Electrical characteristics (Ta=25 °C)
S3901-1024Q
S3904-2048Q
Parameter
Symbol
Condition
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
High V
φ1, Vφ2 (H)
4.5
5
10
4.5
5
10
V
Clock pulse (
φ1, φ2)
voltage
Low
V
φ1, Vφ2 (L)
0-
0.4
0
-
0.4
V
High
V
φs (H)
4.5
V
φ1
10
4.5
V
φ1
10
V
Start pulse (
φst) voltage
Low
V
φs (L)
0
-
0.4
0
-
0.4
V
Video bias voltage *
7
Vb
1.5
V
φ - 3.0 Vφ - 2.5
1.5
V
φ - 3.0 Vφ - 2.5
V
Saturation control gate voltage
Vscg
-
0
-
-
0
-
V
Saturation control drain voltage
Vscd
-
Vb
-
-
Vb
-
V
Cl ock puls e (
φ1, φ2) rise/fall time *8
tr
φ1, trφ2
tf
φ1, tfφ2
-
20
-
-
20
-
ns
Clock pulse (
φ1, φ2) pulse width
tpw
φ1, tpwφ2
200
-
-
200
-
-
ns
Start pulse (
φst) rise/fall time
tr
φs, tfφs
-
20
-
-
20
-
ns
Start pulse (
φst) pulse width
tpw
φs
200
-
-
200
-
-
ns
Start pulse (
φst) and clock pulse
(
φ2) overlap
t
φov
200
-
-
200
-
-
ns
Clock pulse space *
8
X1, X2
trf - 20
-
-
trf - 20
-
-
ns
Data rate *
9
f
0.1
-
2000
0.1
-
2000
kHz
Video delay time
tvd
50 % of
saturation
*9, *10
-
200
-
-
250
-
ns
Clock pulse (
φ1, φ2)
line capacitance
C
φ
5 V bias
-
134
-
-
200
-
pF
Saturation control gate (Vscg)
line capacitance
Cscg
5 V bias
-
63
-
-
87
-
pF
Video line capacitance
CV
2 V bias
-
45
-
-
60
-
pF
*7: V
φ is input pulse voltage (refer to figure 8) .
*8: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more should be
input if the clock pulse rise or fall time is longer than 20 ns (refer to figure 7) .
*9: Vb=2.0 V, V
φ=5.0 V
*10: Measured with C7883 driver circuit.
2


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