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IR3637STRPBF Datasheet(PDF) 11 Page - International Rectifier |
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IR3637STRPBF Datasheet(HTML) 11 Page - International Rectifier |
11 / 21 page IR3637SPBF 11 Rev. 1.1 06/16/05 www.irf.com 6) Place second pole at the ESR zero. FP2 = FESR Check if R8 > If R8 is too small, increase R7 and start from step 2. 7) Place second zero around the resonant frequency. FZ2 = FLC 8) Use equation (1) to calculate R5. These design rules will give a crossover frequency ap- proximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load tran- sient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to - 12dB). The phase margin should be greater than 45 for overall stability. Based on the frequency of the zero generated by ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation type and location of crossover frequency. Layout Consideration The layout is very important when designing high fre- quency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the con- nection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two par- allel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control cir- cuit ground (analog ground), to which all signals are ref- erenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. 1 gm R8 = 1 2 π × C10 × FP2 R6 = - R8 1 2 π × C10 × FZ2 R5 = × R6 VREF VOUT - VREF Compensator Type Type II (PI) Type III (PID) Method A Type III (PID) Method B Location of Zero Crossover Frequency (FO) FLC < FESR < FO < fS/2 FLC < FO < FESR < fS/2 FLC < FO < fS/2 < FESR Typical Output Capacitor Electrolytic, Tantalum Tantalum, Ceramic Ceramic Table - The compensation type and location of zero crossover frequency. Detail information is dicussed in application Note AN- 1043 which can be downloaded from the IR Web-Site. All design should be tested for stability to verify the cal- culated values. |
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