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ADF7012BRU-REEL Datasheet(PDF) 7 Page - Analog Devices |
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ADF7012BRU-REEL Datasheet(HTML) 7 Page - Analog Devices |
7 / 28 page ADF7012 Rev. 0 | Page 7 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADF7012 TOP VIEW (Not to Scale) DVDD 1 CREG1 2 CPOUT 3 TxDATA 4 TxCLK 5 CREG2 RSET AGND DVDD RFOUT 24 23 22 21 20 MUXOUT 6 DGND 7 OSC1 8 OSC2 9 RFGND VCOIN CVCO L2 19 18 17 16 CLKOUT 10 CLK 11 L1 CE 15 14 DATA 12 LE TSSOP 13 Figure 3. Table 4. Pin Functional Descriptions Pin No. Mnemonic Description 1 DVDD Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 2 CREG1 A 2.2 µF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time, but may cause higher spurious noise. 3 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 4 TxDATA Digital Data to Be Transmitted is inputted on this pin. 5 TxCLK GFSK and GOOK only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the ADF7012. The clock is provided at the same frequency as the data rate. The microcontroller updates TxDATA on the falling edge of TxCLK. The rising edge of TxCLK is used to sample TxDATA at the midpoint of each bit. 6 MUXOUT Provides the Lock_Detect Signal. This determines if the PLL is locked to the correct frequency and also monitors battery voltage. Other signals include Regulator_Ready, which indicates the status of the serial interface regulator. 7 DGND Ground for Digital Section. 8 OSC1 The reference crystal should be connected between this pin and OSC2. 9 OSC2 The reference crystal should be connected between this pin and OSC1. A TCXO reference may be used, by driving this pin with CMOS levels, and powering down the crystal oscillator bit in software. 10 CLKOUT A divided-down version of the crystal reference with output driver. The digital clock output may be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio. 11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. 13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 CE Chip Enable. Bringing CE low puts the ADF7012 into complete power-down, drawing < 1uA. Register values are lost when CE is low and the part must be reprogrammed once CE is brought high. 15 L1 Connected to external printed or discrete inductor. See Choosing the External Inductor Value for advice on the value of the inductor to be connected between L1 and L2. 16 L2 Connected to external printed or discrete inductor. 17 CVCO A 220 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7012. This capacitor is necessary to ensure stable VCO operation. 18 VCOIN The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. 19 RFGND Ground for Output Stage of Transmitter. 20 RFOUT The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output should be impedance matched using suitable components to the desired load. See the PA Matching section. 21 DVDD Voltage supply for VCO and PA section. This should have the same supply as DVDD Pin 1, and should be between 2.3 V and 3.6 V. Place decoupling capacitors to the analog ground plane as close as possible to this pin. 22 AGND Ground Pin for the RF Analog Circuitry. 23 RSET External Resistor to set charge pump current and some internal bias currents. Use 3.6 kV as default. 24 CREG2 Add a 470 nF capacitor at CREG to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time and phase noise, but may have stability issues over the supply and temperature. |
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