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CS61318 Datasheet(PDF) 8 Page - Cirrus Logic

Part No. CS61318
Description  E1 LINE INTERFACE UNIT
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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CS61318
8
DS441PP2
2 THEORY OF OPERATION
The CS61318 E1 Line Interface is a fully integrated
transceiver designed for 2.048 Mbps E1 operation.
The device provides an interface to twisted pair or
co-axial media through standard pulse transformers
and matching resistors. For added flexibility, the
device can be controlled through a serial micropro-
cessor interface (Host Mode Operation) or via de-
vice pins (Hardware Mode).
2.1
Operating Modes
The CS61318 can be controlled in stand-alone
hardware interface mode (MODE pin is low), or by
a microcontroller in serial host mode (MODE pin is
high). Additional functionality is available in the
host mode as described in the Serial interface sec-
tion.
2.2
Master Clocks
The CS61318 requires a reference clock for the re-
ceiver and the jitter attenuator. A 2.048 MHz exter-
nal clock can be input to MCLK, or a 4x crystal can
be connected to the on-chip oscillator. This fre-
quency reference should be within +50 ppm of the
nominal operating frequency. Jitter and wander on
the reference clock will degrade jitter attenuation
and receiver jitter tolerance. If MCLK is provided,
the crystal oscillator is ignored.
2.3
Transmitter
The transmitter accepts digital E1 input data and
drives appropriately shaped AMI (Alternate Mark
Inversion) pulses onto a transmission line through
a transformer. The transmit data (TPOS & TNEG
or TDATA) is sampled on the falling edge of the
input clock, TCLK.
Tying TNEG high for more than 16 TCLK cycles
enables unipolar I/O mode. This changes TPOS to
TDATA, RPOS to RDATA, and RNEG to BPV. In
this mode the HDB3 encoder and decoder is en-
abled on both the receive and transmit paths.
The CS61318 drives a 75
Ω or 120 Ω line through
the appropriate transformer and matching resistors.
A summary of transformer and resistor configura-
tions is given in the Applications section at the end
of this datasheet. Using the recommended circuits
will produce E1 pulses compliant to the G.703 tem-
plate shown in Figure 6.
Custom transmit pulse shapes may be implemented
by writing pulse shape coefficients to on-board
pulse shape registers. Custom pulses may be used
to correct for pulse shape degradation or distortion
caused by improper termination, suboptimal inter-
connect wiring, or loading from external compo-
nents such as high voltage protection devices. Use
of this feature is described in the Arbitrary Wave-
form Generation section.
The CS61318 will detect the absence of TCLK, and
will force TTIP and TRING to high impedance af-
ter 175 bit periods, preventing transmission when
269 ns
244 ns
194 ns
219 ns
488 ns
Nominal Pulse
0
10
50
80
90
100
110
120
-10
-20
Percent of
nominal
peak
voltage
Figure 6. Mask of the Pulse at the 2048 kbps Interface




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