10
Am79Q02/021/031 Data Sheet
Power Supply
AGND
Analog ground
DGND
Digital ground
VCCA
+5.0 V analog power supply
VCCD
+5.0 V digital power supply
Two separate power supply inputs are provided to
allow for noise isolation and proper power supply
decoupling techniques; however, the two pins have a
low impedance connection inside the part. For best
performance, all of the +5.0 power supply pins should
be connected together at the connector of the printed
circuit board, and all of the grounds should be
connected together at the connector of the printed
circuit board.
FUNCTIONAL DESCRIPTION
The QSLAC device performs the codec/filter and two-
to four-wire conversion functions required of the
subs cr iber
line
inter f ac e
cir c uitr y
in
telecommunications equipment. These functions
involve converting audio signals into digital PCM
samples and converting digital PCM samples back into
audio signals. During conversion, digital filters are
used to band limit the voice signals. All of the digital
filtering is performed in digital signal processors
operating from a master clock, which can be derived
either from PCLK or MCLK.
Four independent channels allow the QSLAC device to
function as four SLAC devices or two DSLAC
ä
devices. For programming information, each channel
has its own enable bit (EC1, EC2, EC3, and EC4) to
allow individual channel programming. If more than
one Channel Enable bit is High or if all Channel Enable
bits are High, all channels enabled will receive the
p ro gram min g in fo r m ation wr itten ; therefore, a
Broadcast state can be implemented by simply
enabling all channels in the device to receive the
information. The Channel Enable bits are contained in
the Channel Enable register, which is written and read
using Commands 14 and 15. The Broadcast state is
useful in initializing QSLAC devices in a large system.
The user-programmable filters set the receive and
transmit gain, perform the transhybrid balancing
function, permit adjustment of the two-wire termination
impedance, and provide equalization of the receive and
t ransm it p at hs. All program ma ble d ig ital filt er
coefficients can be calculated using the AmSLAC4 or
WinSLAC™ software.
Data transmitted or received on the PCM highway can
be 8-bit companded code (with an optional 8-bit
signaling byte in the transmit direction) or 16-bit linear
code. The 8-bit codes appear 1 byte per time slot,
while the 16-bit code appears in two consecutive time
slots. The compressed PCM codes can be either 8-bit
companded A-law or µ-law. The PCM data is read from
and written to the PCM highway in user-programmable
time slots at rates of 128 kHz to 8.192 MHz. The
transmit clock edge and clock slot can be selected for
compatibility with other devices that can be connected
to the PCM highway.
Three configurations of the QSLAC device are
offered with single or dual PCM highways. The
Am79Q02 and Am79Q021 QSLAC devices with dual
and single PCM highways respectively are available
in the 44-pin packages. The Am79Q031JC QSLAC
device is a single PCM highway version in a 32-pin
PLCC package.
VOUT1–
VOUT4
Outputs
Analog. The received digital data at DRA or DRB is processed and converted to an analog
signal at the VOUT pin. VOUT1 is the output from channel 1, VOUT2 is the output for channel
2, VOUT3 is the output from channel 3, and VOUT4 is the output for channel 4. The VOUT
voltages are referenced to VREF.
VREF
Output
Analog Voltage Reference. The VREF output is provided in order for an external 0.1 µF ca-
pacitor to be connected from VREF to ground, filtering noise present on the internal voltage
reference. VREF is buffered before it is used by internal circuitry. The voltage on VREF is
nominally 2.1 V, and the output resistance is 100 k
Ω ±30%. The leakage current in the ca-
pacitor must be less than 20 nA.
Pin Names
Type
Description
PCM Highway
Programmable I/O
Chopper Clock
Package
Part Number
Dual
Four
Yes
44 PLCC/TQFP
Am79Q02 JC
Single
Five
No
44 PLCC/TQFP
Am79Q021 JC (or VC)
Single
Two
No
32 PLCC
Am79Q031 JC
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