CY28RS480ZXCT datasheet(4/15 Pages) CYPRESS

Part #	CY28RS480ZXCT

Description	Clock Generator for ATI RS480 Chipset

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY28RS480

Document #: 38-07638 Rev. *C

Page 4 of 15

Control Registers

18:11

Command Code – 8 bits

18:11

Command Code – 8 bits

19

Acknowledge from slave

19

Acknowledge from slave

27:20

Data byte – 8 bits

20

Repeated start

28

Acknowledge from slave

27:21

Slave address – 7 bits

29

Stop

28

Read

29

Acknowledge from slave

37:30

Data from slave – 8 bits

38

NOT Acknowledge

39

Stop

Table 3. Byte Read and Byte Write Protocol (continued)

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Byte 0:Control Register 0

Bit

@Pup

Name

Description

7

1

SRC[T/C]5

SRC[T/C]5 Output Enable

0 = Disable (Hi-Z), 1 = Enable

6

1

SRC[T/C]4

SRC[T/C]4 Output Enable

0 = Disable (Hi-Z), 1 = Enable

5

1

SRC[T/C]3

SRC[T/C]3 Output Enable

0 = Disable (Hi-Z), 1 = Enable

4

1

SRC[T/C]2

SRC[T/C]2 Output Enable

0 = Disable (Hi-Z), 1 = Enable

3

1

SRC[T/C]1

SRC[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enable

2

1

SRC [T/C]0

SRC[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enable

1

SRCS[T/C]1

SRCS[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enable

0

1

SRCS[T/C]0

SRCS[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enable

Byte 1: Control Register 1

Bit

@Pup

Name

Description

7

1

REF2

REF2 Output Enable

0 = Disable, 1 = Enable

6

1

REF1

REF1 Output Enable

0 = Disable, 1 = Enable

5

1

REF0

REF0 Output Enable

0 = Disable, 1 = Enable

4

1

PCI0

PCI0 Output Enable

0 = Disable, 1 = Enable

3

1

USB_48

USB_48MHz Output Enable

0 = Disable, 1 = Enable

2

1

RESERVED

1

CPU[T/C]1

CPU[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enable

0

1

CPU[T/C]0

CPU[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enable

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