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When the RTC register values match alarm register settings, the Alarm Flag bit (AF) is set to a 1. If

signal is cleared by a read or write to the Flags register (Address 1FF0h) as shown in Figure 2. The

IRQ

or write to the Flags register, but the flag will not change states until the end of the read/write cycle and

CLEARING IRQ WAVEFORMS Figure 2

CLEARING IRQ WAVEFORMS Figure 3

occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,

however an alarm generated during power-up will set AF. Therefore the AF bit can be read after system

power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates

alarm timing during the battery backup mode and power-up states.