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IDT74ALVCH16901 Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT74ALVCH16901 Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 9 page  INDUSTRIALTEMPERATURERANGE 8 IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY Open VLOAD GND VCC Pulse Generator D.U.T. 500 Ω 500 Ω CL RT VIN VOUT (1, 2) ALVC Link INPUT VIH 0V VOH VOL tPLH1 tSK (x) OUTPUT 1 OUTPUT 2 tPHL1 tSK (x) tPLH2 tPHL2 VT VT VOH VT VOL tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 ALVC Link SAME PHASE INPUT TRANSITION OPPOSITE PHASE INPUT TRANSITION 0V 0V VOH VOL tPLH tPHL tPHL tPLH OUTPUT VIH VT VT VIH VT ALVC Link DATA INPUT 0V 0V 0V 0V tREM TIMING INPUT SYNCHRONOUS CONTROL tSU tH tSU tH VIH VT VIH VT VIH VT VIH VT ALVC Link ASYNCHRONOUS CONTROL LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE VT tW VT ALVC Link CONTROL INPUT tPLZ 0V OUTPUT NORMALLY LOW tPZH 0V SWITCH CLOSED OUTPUT NORMALLY HIGH ENABLE DISABLE SWITCH OPEN tPHZ 0V VLZ VOH VT VT tPZL VLOAD/2 VLOAD/2 VIH VT VOL VHZ ALVC Link TEST CIRCUITS AND WAVEFORMS Propagation Delay Test Circuit for All Outputs Enable and Disable Times Set-up, Hold, and Release Times NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. Output Skew - tSK(X) Pulse Width NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF TEST CONDITIONS SWITCH POSITION Test Switch Open Drain Disable Low VLOAD Enable Low Disable High GND Enable High All Other Tests Open |
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