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LM2502SM Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LM2502SM Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 27 page Functional Description (Continued) OFF PHASE In the OFF phase, both Master and Slave MPL transmitters are turned off with zero current flowing on the MC and MD lines. Figure 7 shows the transition of the MPL bus into the OFF phase. If an MPL line is driven to a logical Low (high current) when the OFF phase is entered it may temporarily pass through as a logical High (low current) before reaching the zero line current state. The link may be powered down by asserting both the Mas- ter’s and Slaves’s PD* input pins (Low). This causes the devices to immediately put the link to the OFF Phase and internally enter a low power state. To avoid loss of data the Master’s PD* input should only be asserted after the MPL bus has been in the IDLE state for at least 20 MC clock cycles. This gives the Slave enough time to complete any write operations received from the MPL bus. CPU INTERFACE COMPATIBILITY The CPU Interface mode provides compatibility between a CPU Interface and a small form factor (SFF) Display or other fixed I/O port application. Two options are allowed: TABLE 4. Modes Mode Description 0 m68 Interface (E, R/W*), 16-bit support 1 i80 Interface (WR*, RD*), 16-bit support It is not required that both the Master and the Slave to be configured in the same mode. For example the Master may be configured as an 80xx (i80) interface while the Slave is configured for an 68xx (m68) interface. Control information is carried over both MD lines. MD0 car- ries the D0–7 data bits while MD1 the D8–15 data bits. See Figure 8. 20093305 FIGURE 6. MPL Power Up Timing 20093306 FIGURE 7. MPL Power Down Timing www.national.com 11 |
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