CY7B9910
CY7B9920
3
IOS
Output Short Circuit
Current[2]
VCC = Max., VOUT
= GND (25
°C only)
–250
N/A
mA
ICCQ
Operating Current Used by
Internal Circuitry
VCCN=VCCQ=Max.,
All Input
Selects Open
Com’l
85
85
mA
Mil/Ind
90
90
ICCN
Output Buffer Current per
Output Pair[3]
VCCN = VCCQ = Max.,
IOUT = 0 mA
Input Selects Open, fMAX
14
19
mA
PD
Power Dissipation per
Output Pair[4]
VCCN = VCCQ = Max.,
IOUT = 0 mA
Input Selects Open, fMAX
78
104[5]
mW
Electrical Characteristics Over the Operating Range (continued)
CY7B9910
CY7B9920
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
Capacitance[6]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 5.0V
10
pF
Notes:
1.
These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected
inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are
achieved.
2.
Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short
circuit protected.
3.
Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B9920:
ICCN = [(3.5+ .17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F
< C
4.
Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 3 for variable definition.
5.
CMOS output buffer current and power dissipation specified at 50-MHz reference frequency.
6.
Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910)
TTL Input Test Waveform (Cy7B9910)
5V
R1
R2
CL
R1
R2
CL
7B9910–5
CMOS AC Test Load (CY7B9920)
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
≤1ns
≤1ns
2.0V
0.8V
Vth =1.5V
80%
Vth =VCC/2
20%
0.0V
≤ 3ns
≤ 3ns
80%
20%
Vth =VCC/2
7B9910–6
CMOS Input Test Waveform (CY7B9920)
VCC
R1=130
R2=91
CL =50 pF (CL = 30pF for –5 and – 2 devices)
(Includes fixture and probe capacitance)
R1=100
R2=100
CL =50 pF (CL =30 pF for –5 and – 2devices)
(Includes fixture and probe capacitance)
VCC
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