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C9835
Document #: 38-07303 Rev. **
Page 6 of 18
Clock Phase
Table 4. Group Timing Relationships and Tolerances
CPU = 66.6 MHz, SDRAM = 100 MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
2.5
500
CPU to 3V66
7.5
500
180 degrees phase shift
SDRAM/DCLK to 3V66
0
500
When rising edges line up
3V66 to PCI
1.5–3.5
500
3V66 leads
PCI to IOAPIC
0
1000
48M (0,1)
Async
N/A
CPU = 100 MHz, SDRAM = 100 MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
5
500
180 degrees phase shift
CPU to 3V66
5
500
CPU leads
SDRAM/DCLK to 3V66
0
500
When rising edges line up
3V66 to PCI
1.5–3.5
500
3V66 leads
PCI to IOAPIC
0
1000
48M (0,1)
Async
N/A
CPU = 133.3 MHz, SDRAM = 100 MHz
Offset(ns)
Tolerance(ps)
Conditions
CPU to SDRAM/DCLK
0
500
When rising edges line up
CPU to 3V66
0
500
SDRAM/DCLK to 3V66
0
500
When rising edges line up
3V66 to PCI
1.5–3.5
500
3V66 leads
PCI to IOAPIC
0
1000
48M (0,1)
Async
N/A
0ns
10ns
20ns
30ns
40ns
66MHz
100MHz
133MHz
CPU CLOCK
DCLK/SDRAM CLOCK
3V66 CLOCK
PCI CLOCK
100MHz
66MHz
33MHz
CPU CLOCK
CPU CLOCK
1.5ns~3.5
Sync
7.5ns
5ns
5ns
2.5ns
IOAPIC CLOCK
33MHz
DCLK/SDRAM CLOCK 133MHz
0ns
0nS
0ns
3.75ns
3.75ns
0ns
Figure 4.
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