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COP87L88RGN-XE Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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COP87L88RGN-XE Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 40 page  Timers (Continued) TIMER T1 TIMER T2 AND TIMER T3 The devices have a set of three powerful timercounter blocks T1 T2 and T3 The associated features and func- tioning of a timer block are described by referring to the timer block Tx Since the three timer blocks T1 T2 and T3 are identical all comments are equally applicable to any of the three timer blocks Each timer block consists of a 16-bit timer Tx and two supporting 16-bit autoreloadcapture registers RxA and RxB Each timer block has two pins associated with it TxA and TxB The pin TxA supports IO required by the timer block while the pin TxB is an input to the timer block The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead The timer block has three operating modes Processor Inde- pendent PWM mode External Event Counter mode and Input Capture mode The control bits TxC3 TxC2 and TxC1 allow selection of the different modes of operation Mode 1 Processor Independent PWM Mode As the name suggests this mode allows the device to gen- erate a PWM signal with very minimal user intervention The user only has to define the parameters of the PWM signal (ON time and OFF time) Once begun the timer block will continuously generate the PWM signal completely indepen- dent of the microcontroller The user software services the timer block only when the PWM parameters require updat- ing In this mode the timer Tx counts down at a fixed rate of tc Upon every underflow the timer is alternately reloaded with the contents of supporting registers RxA and RxB The very first underflow of the timer causes the timer to reload from the register RxA Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB The Tx Timer control bits TxC3 TxC2 and TxC1 set up the timer for PWM mode operation Figure 8 shows a block diagram of the timer in PWM mode The underflows can be programmed to toggle the TxA out- put pin The underflows can also be programmed to gener- ate interrupts Underflows from the timer are alternately latched into two pending flags TxPNDA and TxPNDB The user must reset these pending flags under software control Two control en- able flags TxENA and TxENB allow the interrupts from the timer underflow to be enabled or disabled Setting the timer enable flag TxENA will cause an interrupt when a timer un- derflow causes the RxA register to be reloaded into the tim- er Setting the timer enable flag TxENB will cause an inter- rupt when a timer underflow causes the RxB register to be reloaded into the timer Resetting the timer enable flags will disable the associated interrupts Either or both of the timer underflow interrupts may be en- abled This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output Alternatively the user may choose to interrupt on both edges of the PWM output TLDD12860 – 10 FIGURE 8 Timer in PWM Mode Mode 2 External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above The main difference is that the timer Tx is clocked by the input signal from the TxA pin The Tx timer control bits TxC3 TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin Underflows from the timer are latched into the TxPNDA pending flag Setting the TxENA control flag will cause an interrupt when the timer underflows In this mode the input pin TxB can be used as an indepen- dent positive edge sensitive interrupt input if the TxENB control flag is set The occurrence of a positive edge on the TxB input pin is latched into the TxPNDB flag Figure 9 shows a block diagram of the timer in External Event Counter mode Note The PWM output is not available in this mode since the TxA pin is being used as the counter input clock TLDD12860 – 11 FIGURE 9 Timer in External Event Counter Mode Mode 3 Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block Tx in the input capture mode In this mode the timer Tx is constantly running at the fixed tc rate The two registers RxA and RxB act as capture registers Each register acts in conjunction with a pin The register RxA acts in conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin http www nationalcom 11 |
Similar Part No. - COP87L88RGN-XE |
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Similar Description - COP87L88RGN-XE |
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