MC54/74HCT161A MC54/74HCT163A

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Guaranteed Limit

Symbol

Parameter

Fig

– 55 to 25

_C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)*

1,7

30

24

20

MHz

tPLH

Maximum Propagation Delay Clock to Q

1,7

20

23

28

ns

tPHL

1,7

25

30

32

ns

tPHL

Maximum Propagation Delay Reset to Q (HCT161A Only)

2,7

25

29

33

ns

tPLH

Maximum Propagation Delay Enable T to Ripple Carry Out

3,7

16

18

20

ns

tPHL

3,7

21

24

28

ns

tPLH

Maximum Propagation Delay Clock to Ripple Carry Out

1,7

22

25

28

ns

tPHL

1,7

28

33

35

ns

tPHL

Maximum Propagation Delay Reset to Ripple Carry Out

(HCT161A Only)

2,7

24

28

32

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

2,7

15

19

22

ns

Cin

Maximum Input Capacitance

1,7

10

10

10

pF

* Applies to noncascaded/nonsynchronous clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out

propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine fmax. However,

if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the fmax in the table above is applicable. See

Applications information in this data sheet.

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Gate)*

Typical @ 25

°C, VCC = 5.0 V

pF

CPD

Power Dissipation Capacitance (Per Gate)*

60

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Symbol

Parameter

Fig.

Guaranteed Limit

Unit

Symbol

Parameter

Fig.

– 55 to

25

_C

≤85°C

≤125°C

Unit

tsu

Minimum Setup Time, Preset Data Inputs to Clock

5

12

18

20

ns

Minimum Setup Time, Load to Clock

5

12

18

20

ns

Minimum Setup Time, Reset to Clock

(HCT163A Only)

4

12

18

20

ns

Minimum Setup Time, Enable T or Enable P to Clock

6

12

18

20

ns

th

Minimum Hold Time, Clock to Preset Data Inputs

5

3

3

3

ns

Minimum Hold Time, Clock to Load

5

3

3

3

ns

Minimum Hold Time, Clock to Reset

(HCT163A Only)

4

3

3

3

ns

Minimum Hold Time, Clock to En T or En P

6

3

3

3

ns

trec

Minimum Recovery Time, Reset Inactive to Clock

(HCT161A Only)

2

12

17

23

ns

Minimum Recovery Time, Load Inactive to Clock

2

12

17

23

ns

tw

Minimum Pulse Width, Clock

1

12

15

18

ns

Minimum Pulse Width, Reset

(HCT161A Only)

1

12

15

18

ns

tr, tf

Maximum Input Rise and Fall Times

500

500

500

ns