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UCD7100 Datasheet(PDF) 8 Page - Texas Instruments |
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UCD7100 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 22 page  www.ti.com APPLICATION INFORMATION Supply Current Sensing and Protection Reference / External Bias Supply Input UCD7100 SLUS651A – MARCH 2005 – REVISED MAY 2005 The UCD7100 is part of a family of digital compatible If limiting the rise or fall times to the power device is drivers targeting applications utilizing digital control desired, then an external resistance can be added techniques or applications that require local fast peak between the output of the driver and the load device, current limit protection. which is generally a power MOSFET gate. The external resistor may also help remove power dissi- pation from the package. The UCD7K devices accept an input range of 4.5 V to 15 V. The device has an internal precision linear regulator that produces the 3V3 output from this VDD A very fast current limit comparator connected to the input. A separate pin, PVDD, not connected internally CS pin is used to protect the power stage by to the VDD supply rail provides power for the output implementing cycle-by-cycle current limiting. drivers. In all applications the same bus voltage The current limit threshold is equal to the lesser of supplies the two pins. It is recommended that a low the positive inputs at the current limit comparator. value of resistance be placed between the two pins The current limit threshold can be set to any value so that the local capacitance on each pin forms low between 0.25 V and 1.0 V by applying the desired pass filters to attenuate any switching noise that may threshold voltage to the current limit (ILIM) pin. When be on the bus. the CS level is greater than the ILIM voltage minus Although quiescent VDD current is low, total supply 25 mV, the output of the driver is forced low and the current will be higher, depending on the gate drive current limit flag (CLF) is set high. The CLF signal is output current required by the switching frequency. latched high until the UCD7K device receives the Total VDD current is the sum of quiescent VDD current next rising edge on the IN pin. and the average OUT current. Knowing the operating When the CS voltage is below ILIM, the driver output frequency and the MOSFET gate charge (QG), aver- will follow the PWM input. The CLF digital output flag age OUT current can be calculated from: can be monitored by the host controller to determine IOUT = QG x f, where f is frequency. when a current limit event occurs and to then apply the appropriate algorithm to obtain the desired current For high-speed circuit performance, a VDD bypass limit profile. capacitor is recommended to prevent noise problems. A 4.7-µF ceramic capacitor should be located close to One of the main benefits of this local protection the VDD to ground connection. A larger capacitor with feature is that the UCD7K devices can protect the relatively low ESR should be connected to the PVDD power stage if the software code in the digital pin, to help deliver the high current peaks to the load. controller becomes corrupted and hangs up. If the The capacitors should present a low impedance controller’s PWM output stays high, the local current characteristic for the expected current levels in the sense circuit will turn off the driver output when an driver application. The use of surface mount over-current condition occurs. The system would components for all bypass capacitors is highly rec- likely go into a retry mode because; most DSP and ommended. microcontrollers have on-board watchdog, brown-out, and other supervisory peripherals to restart the de- vice in the event that it is not operating properly. But these peripherals typically do not react fast enough to All devices in the UCD7K family are capable of save the power stage. The UCD7K’s local current supplying a regulated 3.3-V rail to power various limit comparator provides the required fast protection types of external loads such as a microcontroller or for the power stage. an ASIC. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. For The CS threshold is 25 mV below the ILIM voltage. normal operation, place a minimum of 0.22 µF of This way, if the user attempts to command zero ceramic capacitance from the reference pin to current (ILIM < 25 mV) while the CS pin is at ground, ground. for example at start-up, the CLF flag latches high until the IN pin receives a pulse. At start-up it is necessary to ensure that the ILIM pin always greater than the CS pin for the handshaking to work as described The IN pin is a high impedance digital input capable below. If for any reason the CS pin comes to within of accepting 3.3-V logic level signals up to 2 MHz. 25 mV of the ILIM pin during start-up, then the CLF There is an internal Schmitt Trigger comparator which isolates the internal circuitry from any external noise. 8 |
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Similar Description - UCD7100 |
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