ICS950703XFLF-T datasheet(11/24 Pages) ICST

Part #	ICS950703XFLF-T

Description	PROGRAMMABLE TIMING CONTROL HUB FOR P4

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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11 / 24 page

11

Integrated

Circuit

Systems, Inc.

ICS950703

0690D—05/14/04

Table2: Spread Spectrum Select

SS1

SS0

(Byte 1 bit 7)

(Byte 1 bit 6)

0

0.35%

Default

0

1

0.50%

Spread 2

1

0

0.70%

Spread 3

1

1.00%

Spread 4

0.45%

0.75%

1.00%

Note

Spread %

0.32%

Downspread

%

I

2C Table: Frequency Select Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

FS Source

Frequency H/W IIC

Select

RW

Latch

Inputs

IIC

0

Bit 6

FS6

Freq Select Bit 6

RW

0

Bit 5

FS5

Freq Select Bit 5

RW

0

Bit 4

FS4

Freq Select Bit 4

RW

0

Bit 3

FS3

Freq Select Bit 3

RW

0

Bit 2

FS2

Freq Select Bit 2

RW

0

Bit 1

FS1

Freq Select Bit 1

RW

0

Bit 0

FS0

Freq Selcet Bit 0

RW

1

I

2C Table: Spreading, Device Behavior and Output Control Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

SS1

Spread Select 1

RW

0

Bit 6

SS0

Spread Select 0

RW

0

Bit 5

SSEN

Spread Enable

Control

RW

Disable

Enable

0

Bit 4

Reserved

RW

-

0

Bit 3

CPUT/C3

Output Control

RW

Disable

Enable

1

Bit 2

CPUT/C2

Output Control

RW

Disable

Enable

1

Bit 1

CPUT/C1

Output Control

RW

Disable

Enable

1

Bit 0

CPUT/C0

Output Control

RW

Disable

Enable

1

-

51/50

45/44

42/41

See Table 2: Spread

Spectrum Table

-

Byte 1

See Table 1: Quad

Rom

TM Frequency

Selection Table

-

Byte 0

48/47

-

I

2C Table: Output Control Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

PCICLK7

Output Control

RW

Disable

Enable

1

Bit 6

PCICLK6

Output Control

RW

Disable

Enable

1

Bit 5

PCICLK5

Output Control

RW

Disable

Enable

1

Bit 4

PCICLK4

Output Control

RW

Disable

Enable

1

Bit 3

PCICLK3

Output Control

RW

Disable

Enable

1

Bit 2

PCICLK2

Output Control

RW

Disable

Enable

1

Bit 1

PCICLK1

Output Control

RW

Disable

Enable

1

Bit 0

PCICLK0

Output Control

RW

Disable

Enable

1

14

11

9

8

18

17

15

Byte 2

12

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