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MC100ELT23 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100ELT23 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 3 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3–1 REV 3 © Motorola, Inc. 1996 7/96 Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the ELT23 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The ELT23 is available in only the ECL 100K standard. Since there are no PECL outputs or an external VBB reference, the ELT23 does not require both ECL standard versions. The PECL inputs are differential; there is no specified difference between the differential input 10H and 100K standards. Therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a VCC of 5.0V. • 3.5ns Typical Propagation Delay • Differential PECL Inputs • Small Outline SOIC Package • 24mA TTL Outputs • Flow Through Pinouts 1 2 3 4 5 6 7 8 Q0 GND VCC LOGIC DIAGRAM AND PINOUT ASSIGNMENT D0 Q1 D1 D1 D0 PECL TTL MC100ELT23 PIN FUNCTION Qn TTL Outputs Dn Diff PECL Inputs VCC +5.0V Supply GND Ground PIN DESCRIPTION 1 8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-05 |
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