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AS7C33128PFS36A-166TQC Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C33128PFS36A-166TQC Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 13 page  March 2002 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C33128PFS32A AS7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM 3/4/02; v.1.4 Alliance Semiconductor P. 1 of 13 Features • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns •Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns • Fully synchronous register-to-register operation • Single register “Flow-through” mode • Single-cycle deselect • Dual-cycle deselect also available (AS7C33128PFD32A/ AS7C33128PFD36A) • Pentium®1 compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package • Byte write enables • Multiple chip enables for easy expansion • 3.3 core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power down mode •NTD™1 pipeline architecture available (AS7C33128NTD32A/ AS7C33128NTD36A) 1Pentium® is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. Logic block diagram Q0 Q1 128K × 32/36 Memory array Burst logic CLK CLR CE Address DQ CE CLK DQd CLK DQ Byte write registers register DQc CLK DQ Byte write registers DQb CLK DQ Byte write registers DQa CLK DQ Byte write registers Enable CLK DQ register Enable CLK DQ delay register CE Output registers Input registers Power down 4 36/32 17 15 17 17 GWE BWE BWd ADV ADSC ADSP CLK CE0 CE1 CE2 BWc BWb BWa OE A[16:0] ZZ LBO OE FT CLK CLK 36/32 36/32 DQ [a:d] Pin arrangement DQPc/NC DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc FT VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd/NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DQPa/NC NC VDD Note: Pins 1,30,51,80 are NC for ×32 TQFP 14 × 20 mm Selection guide –200 –183 –166 –133 –100 Units Minimum cycle time 5 5.4 6 7.5 10 ns Maximum clock frequency 200 183 166 133 100 MHz Maximum pipelined clock access time 3 3.1 3.5 4 5 ns Maximum operating current 570 540 475 425 325 mA Maximum standby current 160 140 130 100 90 mA Maximum CMOS standby current (DC) 30 30 30 30 30 mA |
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