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AS7C3513-20 Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C3513-20 Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
1 / 10 page March 2001 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C513 AS7C3513 5V/3.3V 32K×16 CMOS SRAM 3/23/01; v.1.0 Alliance Semiconductor P. 1 of 10 Features • AS7C513 (5V version) • AS7C3513 (3.3V version) • Industrial and commercial temperature • Organization: 32,768 words × 16 bits • Center power and ground pins •High speed - 12/15/20 ns address access time - 6,7,8 ns output enable access time • Low power consumption: ACTIVE - 800 mW (AS7C513) / max @ 12 ns - 432 mW (AS7C3513) / max @ 12 ns • Low power consumption: STANDBY - 28 mW (AS7C513) / max CMOS - 18 mW (AS7C3513) / max CMOS • 2.0V data retention • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • 44-pin JEDEC standard package -400 mil SOJ -400 mil TSOP II • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Logic block diagram 32K × 16 Array OE CE WE Column decoder A0 A1 A2 A3 A4 A5 A7 VCC GND Control circuit I/O0–I/O7 I/O8–I/O15 UB LB I/O buffer A6 Pin arrangement 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A7 A8 A9 A10 NC A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A14 A13 A12 44-Pin SOJ, TSOP II (400 mil) 21 22 A11 NC UB LB I/O15 I/O14 2 A3 3 A2 4 A1 1 NC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 A5 A6 OE A4 Selection guide Shaded areas indicate advance information. AS7C513-12 AS7C3513-12 AS7C513-15 AS7C3513-15 AS7C513-20 AS7C3513-20 Unit Maximum address access time 12 15 20 ns Maximum output enable access time 5 7 9 ns Maximum operating current AS7C513 160 150 140 mA AS7C3513 120 110 100 mA Maximum CMOS standby current AS7C513 5 5 5 mA AS7C3513 5 5 5 mA |
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