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HYMP112S64MP8 Datasheet(PDF) 7 Page - Hynix Semiconductor |
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HYMP112S64MP8 Datasheet(HTML) 7 Page - Hynix Semiconductor |
7 / 17 page HYMP112S64(L)MP8 Rev. 0.1/ July 2004 7 Input AC Logic Level AC Input Test Conditions Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(dc) max to VIH(ac) min for rising edges and the range from VIH(dc) min to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Parameter Symbol Min Max Unit Note AC Input logic High VIH(AC) VREF + 0.250 - V AC Input logic Low VIL(AC) - VREF - 0.250 V Symbol Condition Value Units Notes VREF Input reference voltage 0.5 * VDDQ V1 VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS < Figure : AC Input Test Signal Waveform > VSWING(MAX) delta TR delta TF Start of Falling Edge Input Timing Start of Rising Edge Input Timing VIH(dc) min - VIL(ac) max delta TF Falling Slew = Rising Slew = VIH(ac) min - VIL(dc) max delta TR |
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